1. Field of the Invention
The present invention relates to memory systems used in personal computer systems, and more particularly, to memory systems incorporating multiple previously independent systems and which include the capability for enabling and disabling portions of the memory system.
2. Description of the Prior Art
Personal computer systems are becoming more prevalent. Early personal computers used an 8 bit microprocessor and could address 64 kbytes of memory. While by current standards this seems wholly inadequate, at the time it was a major advance and allowed many previously difficult operations to be performed.
The electronic component manufacturers continued to make advances and personal computer users developed more powerful applications which began to push the limits of the available designs. Intel Corporation introduced the 8088 and 8086 microprocessors, which were 16 bit machines and could address 1 Mbyte of memory. Thus, significantly more computing power became available for use on personal computers. A number of early personal computers were designed using the 8088 and 8086 microprocessors and then International Business Machines Corporation (IBM) introduced the IBM PC, which utilized the 8088 microprocessor. This started the move forward to the current state of personal computers. Applications were developed for the IBM PC which were much more capable than the applications for the 8 bit personal computers. Thus the demand for the IBM PC grew and as the demand grew, more and more powerful applications were developed which soon pushed the PC, and the related PC/XT, to its limits.
Intel Corp. introduced the 80286 microprocessor which could address 16 Mbytes of memory and had significantly greater capabilities than the 8088 or 8086 microprocessors. IBM proceeded to develop and introduce the IBM AT which used the 80286 microprocessor. However, through the AT was more capable than the PC, the addressable random access memory space was still limited to 640 kbytes because of limitations in the operating system. A technique called expanded memory was developed which allowed access to physical memory beyond the 640 kbyte logical limit.
During this evolution of personal computers the sizes of available memory circuits increased. In the early 8 bit personal computers 16 kbit dynamic random access memories (DRAM's) were utilized An array of 32 or 36 circuits covered the entire memory space of the microprocessor and could easily fit on one circuit board. Sixty-four kbit DRAM's became available at approximately the same time as the 8086, thus allowing the increased memory space to be utilized. However, 90 circuits were required to fill the 640 kbytes of memory available under the operating system. These 90 circuits could not be placed on one small circuit board and so a plurality of boards having fewer DRAM's were utilized. The starting logical address of each board was set by switches or jumpers. This was not unreasonable at the time because the system integrators were generally very skilled and the number of options or possibilities was limited. The advent of the AT, expanded memory, and the 256 kbit DRAM changed this situation. Now 16 Mbytes of memory were available, with 567 256 kbit DRAMS's needed to completely fill the available address space for RAM. The physical space available on a given circuit board limited the amount of the memory a single circuit board could provide, so the addressing setup became much more complicated, particularly as more circuit boards were installed in the computer system. The expanded memory technique further dramatically complicated the situation by adding yet another layer of possibilities. A final layer of complexity was added by the need to disable portions of the circuit board if some memory circuits failed or were not placed in the circuit board. But setup and location of the memory was still done by switches and jumpers and the average skill level of the integrator had reduced as more users began assembling the computer system themselves. Thus many problems occurred trying to get memory boards properly installed. The use of 1 Mbit DRAM's partially simplified problems because fewer boards were needed for a given amount of memory, but the boards still had to allow for all possibilities, so the simplification was relatively minor.
As a perceived response to the demand for more capabilities in personal computers, IBM introduced the Personal System/2 family of personal computers. These systems used a different architecture, referred to as the MicroChannel Architecture or MCA, as compared to the architecture of the AT, referred to as the Industry Standard Architecture or ISA. For more information on the MCA, please refer to the IBM Corp. publication entitled "Personal System/2 Model 80 Technical Reference", having a publication date of April 1987.
One change made by IBM in moving from the ISA to the MCA was the specification of Programmable Option Select or POS registers. These registers allowed setup of circuit boards to be performed without the need for setting switches or jumpers. Various values written to these registers would be interpreted by the circuit board and the appropriate options set. For memory circuit boards the POS technique allowed the reading of the amount of memory installed on each circuit board. The total amount and configuration of the memory could thus be determined. After this determination was made, appropriate values were written to the POS registers to set the starting address of a memory board and which 1 Mbyte banks were enabled on the memory board.
When such a computer system was developed by IBM a standard 32 bit memory board was used. This memory board had a limit of 6 Mbytes of memory. To this end only six enable signals were defined in the POS registers, one for each 1 Mbyte bank of memory. If such boards were used in a computer system, several boards were necessary to reach the 16 Mbyte memory limit of an 80286 microprocessor. Three individual card slots were allocated to reach this 16 Mbyte limit, with an amount of memory, for example 1 or 2 Mbytes, being located on the system board. This need for potentially three slots dedicated to memory either required the use of a larger number of total slots if an acceptable number of non-memory slots were to be provided, thus increasing the overall size of the computer system, or the reduction in the number of non-memory slots or locations to below acceptable limits.
One overriding concern should the amount of memory on a given board be changed is compatibility with previous designs, particularly the IBM memory board design. Merely changing the amount of memory available on the board could have an adverse affect on compatibility, thus decreasing the usefulness of the revised board, unless all the desired applications programs and operating programs understood the different design. For example, if the memory size was doubled, the POS configuration and setup programs would not function properly. Because of limited numbers and codings of the values read to determine memory size, the POS configuration programs could not interpret values greater than 6 Mbytes. This presented a major problem because this would require a circuit board manufacturer to rewrite operating or machine specific programs. Additionally, the limit imposed by the number of lines available to enable or disable memory blocks would force a change in block size to greater than 1 Mbyte. This also creates problems with the POS setup programs. Thus, merely adding memory to a given board was not a viable solution.
The capability of enabling and disabling 1 Mbyte memory blocks required a way to determine which blocks were disabled and compare the resulting effective address of each block with the presented memory address to determine which memory circuits to use. When IBM developed its 32 bit memory board, the primary means of determining which set of memory circuits to utilize when a memory access was requested was through the use of programmable array logic devices (PAL's). The PAL's were encoded with all the terms representing the possible active states for the row address signals needed for use with DRAM's. This use of PAL's restricts any expansion of the design if the preferred 1 Mbyte enable block size is to be retained because of the number of terms present in PAL's available. Continuing the full possibility logic for more than six blocks as done by IBM results in using a very large number of PAL's and space at great cost, thus complicating the design of the memory circuit selection logic and increasing the cost.